IEEE Build-Up Substrate Symposium (BUSS)

Substrate Technologies: New Innovations, Challenges, Financing

BUSS’25 is a two-day, in-person event — May 8-9, 2025 in Silicon Valley, CA USA

View our developing 2025 program Registration is NOW OPEN

We are living in the era of heterogeneous integration driven by fast, efficient and big data computing resources at our fingertips. The mega-monolithic silicon chip is a thing of the past, replaced with 3D heterogeneous integration of chiplets onto a platform made of an organic build-up substrate. Volume manufacturers of build-up substrates are entirely based in Asia, leaving a desert in the US. Volume build-up substrates used by major IDMs are manufactured in Asian countries including Taiwan, Japan and China.
However, there are multiple activities starting up in the US, and this is why a gathering of the US players is important. This symposium is geared for all those involved in the supply chain of build-up substrates in the US, as well as users. As the US Congress debates H.R. 3249, the Protecting Circuit Boards and Substrates (PCBS) Act, this Symposium is an opportunity for all build-up substrate players to meet, network and cohesively work with funding agencies who will be invited to this symposium to focus on onshoring build-up substrate production and utilization.

Sessions:

— Substrate Challenges for Chiplet Integration
— Materials for Substrates
— Emerging Substrate Technologies
— Panel Equipment and Technologies for Substrates
— Design Integrations
— Metrology

… plus two panels:
— The Gap Between US and Overseas Substrate Manufacturing
— Technology Development R&D Centers of Excellence

PLAN TO ATTEND in 2025!

Confirmed Speakers at BUSS:

Substrate Market Outlook Jan Vardaman, TechSearch Int’l	Advanced Packaging Substrate Technologies for Power Efficient AI Products Sai Boyapati, AMD Advanced Packaging	Large Scale Glass Substrate for High Performance Computing Application Satoru Kuramochi, Dai Nippon Printing Co.
Dry-film Solder Resist Materials for High Density IC Substrates Yuya Suzuki, Taiyo America	Advanced Photo-imageable Dielectric Film Enabling Sub-5-micron Patterning Hikaru Mizuno, JSR Micro	Substrate Materials for Advanced Packaging Masa Fukui, Resonac America, Inc.
Wafer-Level Si Core Substrates – Third Leg of the NAPMP Substrates Program Steven Verhaverbeke, Applied Materials	Next Generation Organic Substrate Technology: How Will it Synergize with 2.5D? Omar Bchir, Qualcomm	Addressing Advanced Packaging Scaling and Yield Challenges with Mask-less Lithography Niranjan Khasgiwale, Applied Materials
Accelerating Advanced IC Substrate Development with Versatile Process Control Solutions Monita Pau, Onto Innovation	Addressing New Challenges with Conventional Organic Substrates Venkata Mokkapati, AT&S AG	Advanced Inspection and Metrology for Glass Panel Processing Barton A. Katz, Nanospan Technologies
*… and many more!* See the full listing