Accepted Papers

    • Tawfik Rahal-Arabi, Paul Van der Arend, Ashish Jain, Mehdi Saidi, Rashad Oreifej, Sriram Sundaram and Rajit Seahra. Optimizing Power and Power Delivery For Data Center GPUs
    • Sylvester Ankamah-Kusi, Blake Travis, Swathi Kamath, Rajen Murugan and Tom Kronenberg. Electrothermal Co-Design Modeling and Analysis of an Ultra-Low On-Resistance Power Switch
    • Nasirul Chowdhury, Jon Guerber, Yin-Huan Hwang, Takao Oshita, Anindya Saha and Allen Waters. 8.4GTS LPDDR5x and 5.6GTS DDR5 Combo PHY
    • Jongchul Shin, Hamid Eslampour, Sangnam Jeong, Woopoung Kim, Seokbeom Yong, Sung-Oh Ahn, Eunkyeong Park and Sangsub Song. Signal Integrity of Die-to-Die Interface with Advanced Pacakges for Co-Packaged Optics
    • Alexander Kirchberger and Anestis Dounavis. Delay Rational Macromodelling of Noisy Tabulated Frequency Responses
    • Dan Liu, Yangfan Zhong, Minzheng Tian, Mengmeng Guo, Bing Wei, Weizhe Li, Jingbo Li and Tina Bao. Fan-out Region Crosstalk Optimization of High-Density PCIe 6.0 SMT Connectors
    • Yen-Tung Chen, Yu-Ying Cheng and Tzong-Lin Wu. Optimization of TSV Array Based on Mathematical Model for HBM3
    • Chad Smutzer, Jordan Keuseman, Alexander Hickman and Clifton Haider. Application of the Reverse Pulse Technique for Worst Case Transient Analysis in HPC PDN Design
    • Aobo Li, Jun Wang, Yan Xu, Kangkang Zhang and Xiuqin Chu. A DDR5 Interposer De-embedding Method Based on Transfer Function
    • Paolo Manfredi and Riccardo Trinchero. A Hybrid Polynomial Chaos Expansion and Gaussian Process Regression Method for Forward Uncertainty Quantification of Integrated Circuits
    • Lihong Feng, Vinayak Bansal, Valentin de la Rubia and Peter Benner. Parametric S-Parameter Prediction Using Deep Learning
    • Samuel Elkin, Michael Haider and Thomas Roth. Modeling Multiplexed Qubit Readout with a Josephson Traveling-Wave Parametric Amplifier
    • Oluwafemi Akinwale, Dan Liu, Kai Wang, Yangfan Zhong, Cesar Mendez-Ruiz and Kusuma Matta. Comparative Evaluation of 100G-PAM4 Ethernet Link Performance in Air and Immersion Cooling Conditions
    • Zhekun Peng, Junyong Park, Sathvika Bandi, Santosh Pappu, Srinivas Venkataraman, Xu Wang, Granthana Rangaswamy and Donghyun Kim. Cascading of 2D and 3D Simulations of ASIC Substrate Interconnect up to 100 GHz
    • Rajen Murugan, Jie Chen, Guangxu Li, Suzuki Yutaka and Sylvester Ankamah-Kusi. Multiphysics Simulation and Measurement Correlation of a Multichip Module IC Package Current Sensor
    • Mehdi Mousavi, Kevin Cai, Junyong Park, Chaofeng Li, Reza Asadi, Shameem Ahmed, Bidyut Sen, Donghyun Kim and Manish K. Mathew. Impact of Non-Functional Pads Location on Eye Diagram Performance
    • Keeyoung Son, Seonguk Choi, Keunwoo Kim, Jiwon Yoon, Junghyun Lee, Haeseok Suh, Hyunjun An and Joungho Kim. High-speed Interconnect Design of Silicon Interposer based Heterogeneous Integration for AI Computing
    • Haeseok Suh, Jiwon Yoon, Keeyoung Son, Seonguk Choi, Keunwoo Kim, Junghyun Lee, Taein Shin, Hyunjun An, Taesoo Kim, Jungmin Ahn, Hyunah Park, Hyunsik Kim, Taeil Bae, Haekang Jung and Joungho Kim. Design and Analysis of L3 Cache Embedded-GPU-High Bandwidth Memory Architecture with Reduced Energy and Latency for AI Computing
    • Byung Cheol Min, Mun Ju Min, Hyun Chul Choi and Kang Wook Kim. Analysis of Nonlinear Phase Interactions of a Differential Line in the Presence of a Signal Skew
    • Mulat Ayinet Tiruye, Olani Baissa Gerba and T. Hui Teo. A 155 MHz Low-Jitter PLL for Enhanced Signal Integrity in High-Speed Interconnects
    • Soshi Shimomura, Yutaka Uematsu, Katsuya Kikuchi, Haruo Shimamoto, Yuuki Araga and Shinichi Ouchi. Single-Layer Wiring Design in UCIe to Realize Low-Cost Interposer Substrate
    • Jinwook Song, Jinan Lee, Jonghee Jeong, Seokwoo Hong, Sungwoo Jin, Sungwon Roh, Taehyun Shim, Juneyoung Kim, Sunghoon Chun, Hyunwoo Kim, Chorom Jang, Youngjun Ko, Dongho Choi and Kyungsuk Kim. PCIe Gen 6.0 SSD Receiver PAM 4 SI Analysis Based on End Port Time domain Measurements for Unknown System Channel
    • Eric Bracken. Using Generative AI to Predict DC Electrical Performance
    • Youngjun Ko, Jinwook Song, Seokwoo Hong, Jinan Lee, Jonghee Jeong, Hyunwoo Kim, Chorom Jang, Sungwoo Jin, Sungwon Roh, Dongho Choi, Kyungsuk Kim and Sunghoon Chun. PCIe Gen 6.0 SSD PSIJ Estimation Based on Early Design Stage Jitter Sensitivity Measurements
    • Sungwoo Jin, Jinwook Song, Seokwoo Hong, Youngjun Ko, Hyunwoo Kim, Sungwon Roh, Chorom Jang, Dongho Choi, Kyungsuk Kim and Sunghoon Chun. Application of CAMM2 Connector on PCIe Gen 6.0 SSD Host Interface for Low Near-End Crosstalk
    • Hyunwoo Kim, Dongryul Park, Seunghun Ryu, Seonghi Lee, Sanguk Lee, Jinwook Lee, Dongkyun Kim and Seungyoung Ahn. An Efficient SPICE-compatible Model for Fast Co-simulation of Signal and Power Integrity on Multilayer PCB with Arbitrary Shape
    • Yi Zhou and José Schutt-Ainé. Latency Insertion Method for Fast Electro-Thermal Simulation of FinFET with Self-Heating Effect
    • Hyunjun An, Junghyun Lee, Keeyoung Son, Seonguk Choi, Taein Shin, Keunwoo Kim, Jiwon Yoon, Taesoo Kim, Jungmin Ahn, Hyunah Park, Haeseok Suh and Joungho Kim. Eye-Diagram Edge Estimation (EEE) Network for Through Silicon Via Design in Next-Generation High Bandwidth Memory
    • Germin Ghaly, Emad Gad and Michel Nakhla. Automated Accurate Quadratic Formulation of Nonlinear Circuits
    • Sungjin Yoon, Manho Lee, Kwangho Kim, Hyeongi Lee, Chulhee Cho, Youngjae Lee, Wooshin Choi, Young-Chul Cho, Jung-Hwan Choi and Young-Soo Sohn. Crosstalk Analysis in Add-In Card structure for High-Speed SerDes Channels with PCIe Gen6
    • Zhu-Chen Chang, Chien-Min Lin and Ruey-Beei Wu. Agile Analysis for Worst-Case Eye-Diagrams in Multi-Line Links of CoWoS Packaging
    • Lambert Simonovich. Deducing Dk Anisotropy in Glass-Reinforced PCB Substrates from Laminate Construction Tables Using Heuristic Methods
    • Pascal den Boef, Wil Schilders, Joseph Maubach, Nathan van de Wouw and Diana Manvelyan. Operator Inference for Rigid-Flex Printed Circuit Boards Subject to Large Deformations
    • Andrew Page and Matteo Cocchini. A Signal Integrity Comparison of VIPPO Technology for PCIe 5.0 DC Blocking Capacitors
    • Lu Qiu, Xiao-Wei Zhu and Xian-Long Yang. Analysis of Interconnects in Multilayer SIW Bandpass Filters Design
    • Ram Krishna, Ashita Victor, Srujan Penta, Xu Chen, Muhannad Bakir, Nam Sung Kim and Elyse Rosenbaum. Yield-Aware Interposer Design for UCIe Interconnects
    • Cheng-Yuan Lu, Chien-Min Lin and Ruey-Beei Wu. Efficient Thermal Analysis for Heat Dissipation in Three-Dimensional Chip-Stacking Packaging
    • Mun-Ju Kim, Byung-Cheol Min, Hyun-Chul Choi and Kang-Wook Kim. Design of an Ultra-High-Speed Digital Interface Based on a Coplanar Stripline
    • Asha Jakhar, Rohit Sharma, Avirup Dasgupta and Sourajeet Roy. Spacer Optimization using a Neuro-PSO Approach for Improving FinFET Repeater Performance in On-Chip Global MLGNR Interconnects
    • Haeyeon Kim, Joonsang Park, Hyunah Park, Keeyoung Son, Hyunsik Kim, Taeil Bae, Haekang Jung and Joungho Kim. Design and Analysis of High-Density Silicon Interposer Channel and Power Distribution Network
    • Junghyun Lee, Keeyoung Son, Junho Park, Joonsang Park, Keunwoo Kim, Hyunjun An, Seonguk Choi, Jihun Kim, Hyunah Park, Sumi Choi, Sanghyuk Son and Joungho Kim. Signal Integrity Analysis of PCIe Channel with Floating Board-to-Board Connectors in Automotive Infotainment System
    • Hyunah Park, Seonguk Choi, Haeyeon Kim, Taein Shin, Keeyoung Son, Jiwon Yoon, Junghyun Lee, Haeseok Suh, Taesoo Kim, Jungmin Ahn, Hyunjun An and Joungho Kim. Design and Analysis of Extended Scale Cache (ESC) Stacked-GPU-HBM Module Architecture Considering Power Integrity (PI)
    • Keunwoo Kim, Hyunwook Park, Keeyoung Son, Seonguk Choi, Taein Shin, Junghyun Lee, Jiwon Yoon, Hyunjun An, Haeyeon Kim, Wooshin Choi, Jung-Hwan Choi and Joungho Kim. Explainable Reinforcement Learning(XRL)-based Decap Placement Optimization for High-Bandwidth Memory (HBM)
    • Antonio Carlucci and Stefano Grivet-Talocia. Nonlinear macromodeling of voltage-regulated power delivery networks
    • Tommaso Bradde, Antonio Carlucci, Riccardo Trinchero, Paolo Manfredi and Stefano Grivet-Talocia. Efficient parametric assessment of worst-case voltage droop in power delivery networks
    • Katharina Scharff, Xiaomin Duan and Dierk Kaller. Limit of the Impact of the Via Stub Length on the Via Impedance in Printed Circuit Boards
    • Felix Yuan and Abinash Roy. Reinforcement Learning Based Automatic Router for Power Delivery Network Prototypes
    • Xinlin Tang, Shuxiang Li, Tao Fang and Yuan Fang. Improve CLK Phase Noise Performance by Mitigating Antiresonance Phenomenon of Power Net with a π-Type Filtering Structure
    • Festim Iseini, Han-Ting Lin, Nicola Pelagalli, Andrea Malignaggi, Corrado Carta, Gerhard Kahmen and Andreas Weisshaar. A Tunable Inductor Peaking Technique for Optical Communication Systems
    • Han-Ting Lin, Festim Iseini and Andreas Weisshaar. Tunable True-Time-Delay Unit Based on Bridged T-Coil
    • Ahsan Javaid, Ramachandra Achar and Jai Tripathi. An Efficient Machine Learning Approach for PSIJ Analysis in a Chain of CMOS Inverters
    • Thijs Ullrick, Dirk Deschrijver, Wim Bogaerts and Tom Dhaene. Modeling Microwave S-parameters using Frequency-scaled Rational Gaussian Process Kernels
    • Taein Shin, Seonguk Choi, Jungmin Ahn, Keunwoo Kim, Junghyun Lee, Haeseok Suh, Hyunah Park, Haeyeon Kim, Hyunjun An, Jinwook Song and Joungho Kim. PSIJ based Optimal PDN Design for Cost-Effective SSD using Reinforcement Learning
    • Shuxiang Li, Xinlin Tang, Tao Fang, Yuan Fang, Greg Fu and Stephen Scearce. A Study on How Capacitance of Power Filtering Circuit Influences the Antiresonance Frequency
    • Silvia Simone, Fabio Pareschi, Davide Lena and Gianluca Setti. Simulation method for Quasi-static solver to effectively model parasitic components between Package and PCB
    • Tong Liu and Samuel Palermo. Analysis of Echo and Crosstalk Cancellation in Simultaneous Bidirectional Transceivers for Dense Die-to-Die Interconnects
    • Jie Chen, Rajen Murugan, Vishnu Ravinuthula, Willy Bristiel, Bibhu Nayak, Harikiran Muniganti and Dipanjan Gope. Modeling and Analysis of IC Pin-Level Voltages for Bulk Current Injection (BCI) Testing
    • Priyank Kashyap, Yeujiang Wen, Yongjin Choi, Chris Cheng and Paul Franzon. Transformer Based Channel Identification
    • Jungmin Ahn, Seonguk Choi, Taein Shin, Junghyun Lee, Jiwon Yoon, Keunwoo Kim, Keeyoung Son, Haeseok Suh, Taesoo Kim, Hyunah Park, Hyunjun An, Jinwook Song and Joungho Kim. Design and Analysis of Ultra High Bandwidth (UHB) Interconnection-based GPU-Ring for the AI Superchip Module
    • Jonatan Aronsson and Feng Ling. Recent Advances in Signal Integrity Simulation and Analysis of Interposers
    • Vinicius C. Do Nascimento, Seunghyun Hwang, Michael Smith, Qiang Qiu, Cheng-Kok Koh, Ganesh Subbarayan and Dan Jiao. Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
    • Martijn Huynen, Vladimir Okhmatovski, Daniël De Zutter and Dries Vande Ginste. Accuracy Study of the Differential Surface Admittance Operator for Lossy Metal Characterization
    • Stefan de Araujo, Daniel de Araujo and Bhyrav Mutnury. Compact Fiber Weave Model for Full Wave Solvers
    • Stefan de Araujo, Daniel de Araujo, Roger Delbue and Ryan Keegan. Megtron 6 and 8 Characterization Methodology
    • Alireza Niazi and Vladimir Okhmatovski. Full-Wave Analysis for Ground Via Placement with Layered Media Integral Equations
    • Doganay Ozese, Mustafa Gökçe Baydoğan, Ahmet Durgun and Kemal Aygun. Tree-Based Boosting for Efficient Estimation of S-Parameters for Package Electrical Analysis
    • Hasan Said Unal and Ahmet Cemal Durgun. Causal RL Prediction of Fine-Pitch Interconnects Using Neural Networks
    • Anandajith Jinesh and Xuan Chen. A robust optimization approach for High Bandwidth Memory interposer using Machine Learning
    • Anuj Mathur and Ramachandra Achar. Hand-drawn Circuit Schematic Digitization and Netlisting using Machine Learning with Emphasis on Signal Integrity Applications
    • Mohamed Bellaredj, Goran Miskovic and Luka Vojkuvka. Analysis and Modeling of Controlled Silicon Substrate Roughness for Silver-Based Backside Metallization in Power Electronics Packaging
    • Mohamed Sahouli, Isaac Ali, David Reinamendivil and Gerry Talbot. Worst-Case Voltage Droop Using Peak Distortion Analysis
    • Shakib Mahmood, Parneet Tethy, Richelle L. Smith, Carl W. Werner and Masum Hossain. Equalization Techniques for Time Domain Signalling
    • Damian Marek, Jasper Hatton, Yongzhong Li and Piero Triverio. A Highly-Scalable Parallel Boundary Element Method for the Full-Wave Electromagnetic Analysis of Large Interconnect Networks and Entire Packages
    • Karanvir Singh Sidhu and Roni Khazaka. Gradient-based method to find solution for Rational Polynomial Chaos coefficients for Uncertainty Quantification
    • Yongzhong Li and Piero Triverio. On the Parallelization of the MultiAIM Algorithm for the Fast Electromagnetic Analysis of 3D ICs