Keynote/Plenary Sessions

Keynote 1: Dr. Hakaru Tamukoh

Associate Professor, Ph.D.
Department of Brain Science and Engineering, Graduate Schoolo of Life Science and Systems Engineering (LSSE), Kyushu Institute of Technology (Kyutech).

Title:

Hardware Accelerators for Brain-Like Artificial Intelligence on Home Service Robots

In recent years, service robots have become increasingly common. We develop home service robots Exi@ and Toyota HSR and attend RoboCup@Home that is an annual and the largest worldwide competition for home service robots. In this competition, robots perform practical applications in public and residential environments, e.g., acting as a waiter in a restaurant and tidy-up a children room. To realize such applications, robots require the implementation of intelligent processing, such as object recognition and detection, speech recognition, autonomous navigation and so on, and a significant number of intelligent processes run simultaneously. Therefore, the computing resources of embedded computers in a robot are always insufficient. In this talk, we briefly review the latest artificial intelligence for home service robots and our activities in RoboCup@Home competition. Then, we present a brain-inspired amygdala neural network model that learns preferences through human-robot interactions. Finally, we propose a “connective object for middleware to accelerator (COMTA),” which is a processing system that uses field programmable gate arrays (FPGAs) as hardware accelerators, and show examples of applications accelerated by COMTA for home service robots.

Keynote 2: Dr. Nattha Jindapetch

Associate Professor, Ph.D.
Department of Electrical Engineering, Faculty of Engineering, Prince of Songkla University, Thailand

Title:

A Review of Design Methodologies for Heterogeneous FPGA-CPU Platforms

Recently, heterogeneous FPGA-CPU platforms are well suitable for adaptable and intelligent systems such as artificial intelligence (AI), 5G infrastructure, network interface card (NIC), software-defined networking (SDN), network function virtualization (NFV), data analytic, media processing, and advanced driver assistance systems (ADAS). The challenge is how developers bring their products to market quickly using existing design methodologies. For C/C++ software development, Xilinx offers SDAccel, SDSoC, and embedded development environments whereas Intel has HLS Compiler, SDK for OpenCL, SoC embedded development suite. For hardware development, Xilinx offers Vivado design suit whereas Intel has Quartus Prime. For system development, Xilinx offers System Generator for DSP whereas Intel has DSP Builder for Intel FPGAs. Moreover, Mathworks support model, verify, and program algorithms on FPGAs without writing any code. This talk will review these tools in more details.

 

Keynote 3: Dr. Bambang Sunaryo Suparjo

SoC Design Engineer, Ph.D.
Intel Corp. Hillsboro Oregon

Title:

Challenges in SoC DFT Implementation

As the die size increases and transistor dimension shrinking, more and more IPs and application blocks can be integrated into a single SoC (system-on-chip) device. While this achievement offers great advantages to the overall system features and performance, it however introduces challenges in DFT (design-for-test) physical implementations. Test data needs to be applied from chip external ports to the interface pins of internal IPs and blocks located deep down multiple hierarchy levels. Similarly the test measured data needs to be delivered from the IPs and blocks to the chip external ports. With the industrial practice of chip physical abutted IPs and blocks placement, test data paths need to be fed through dedicated channel blocks or application blocks to reach their destinations. The longer the paths, the bigger challenges for the test data propagation to meet the expected timing closure. Implementing pipeline stages along the test data paths introducing another challenge on the clocking architecture. For these reasons, early DFT implementation planning that involved both DFT and physical teams is needed to ensure the chip able to be implemented on time. This lecture discusses DFT implementation challenges and planning.

 

Keynote 4: Dr Wan Zuha Wan Hasan

Associate Professor, Ph.D.
Department of Electrical and Electronics Engineering, Faculty of Engineering, Universiti Putra Malaysia, Malaysia

Title:

Soft Robotic Hand Glove for Rehabilitation

About 15% of the world population have some form of disabilities which suffers for daily activities due to cerebral vascular accident (CVA) or stroke. Enhancing the wearable lightweight robotic hand glove that able to enhance rehabilitation process as well as the mechanism of secured grasping objects is essential to reduce this suffer. Since, commercial robotic gloves only used for normal grasping mechanism which no feedback response to assist the paralysed hands. Thus, introducing a wearable robotic hand gloves based on pressure sensors or sEMG for rehabilitation system is required for nowadays quality of life. These new approaches provide a real time self-calibration and muscle activities methods of wearable robotic hand glove in order to improve the efficiency of measurement. Results shown that high accuracies measurement which lead to reduce the cost and the size of such systems and make them more affordable and practical both grasping mechanisms and rehabilitation activities.