MINI COLLOQUIUM
In-person sessions will take place at the Intercontinental Hotel in Puebla.
Date: July 2, 2023.
Cor Claeys
Fellow IEEE, Fellow ECS
Distinguished Lecturer IEEE EDS
Leuven, Belgium
Cor Claeys
BIOGRAPHY:
Cor Claeys is Professor at the KU Leuven (Belgium) since 1990. He was with imec, Leuven, Belgium from 1984 till 2016 and had different positions including, Director Strategic Relations. His main interests are semiconductor technology, device physics, low frequency noise phenomena, radiation effects and defect engineering. He is teaching a variety of short courses in different parts of the world (Europe, China, India and Brazil).
He co-edited books on “Low Temperature Electronics” and “Germanium-Based Technologies: From Materials to Devices” and wrote monographs on “Radiation Effects in Advanced Semiconductor Materials and Devices”, “Fundamental and Technological Aspects of Extended Defects in Germanium”, “Random Telegraph Signals in Semiconductor Devices” and “Metals in Silicon- and Germanium-Based Technologies: Origin, Characterization, Control and Electrical Impact”. Two books are translated in Chinese. He (co)authored 16 book chapters, over 1200 conference presentations and more than 1400 technical papers (of which more than 430 in peer-reviewed scientific journal). He is editor/co-editor of 70 Conference Proceedings.
Prof. Claeys is a Fellow of the Electrochemical Society and of IEEE. He was Founder of the IEEE Electron Devices Benelux Chapter, Chair of the IEEE Benelux Section, elected Board of Governors Member and EDS Vice President for Chapters and Regions. He was EDS President in 2008-2009 and Division Director on the IEEE Board of Directors in 2012-2013. He is a recipient of the IEEE Third Millennium Medal and received the IEEE EDS Distinguished Service Award. He is a Distinguished Lecture of the IEEE Electron Devices Society. Within the Electrochemical Society, he was Chair of the Electronics & Photonics Division (2001-2003) . In 2004, he received the Electronics & Photonics Division Award. In 2016 he received the Semi China Special Recognition Award for outstanding involvement in the China Semiconductor Technology International Conference (CSTIC).
TRENDS AND CHALLENGES IN MICRO- AND NANOELECTRONICS FOR THE NEXT DECADE
Semiconductor technology knowns an exponential evolution in the last decades and is fully integrated in our everyday life. According to the Semiconductor Industry association (SIA) the global semiconductor industry sales reaches US$ 600 billion in 2022, corresponding with a shipment of more than 1.2 trillion components. This necessitated implementation of many novel materials, advanced design concepts and new transistor structures.
Increased device performance and reduced power consumption, while maintaining a good manufacturability and yield performance without penalizing the cost/function, are driving microelectronic research towards 3-nm technologies. A large variety of device architectures such as FinFETs, TFETs, negative capacitance, Gate-All-Around, nanowires (NWs), nanosheets (NSs) in both horizontal or vertical configurations, CFET and Forksheet structures are extensively investigated for both logic and analog/RF building blocks enabling System-on-Chip (SoC) applications. Innovative heterogeneous Ge and III-V technologies on
a Si platform are also gaining interest. Wide bandgap materials such as III-nitrides have a strong potential for RF and power parts. Increased system functionality and density is achieved by 3D integration based on Through Silicon Vias (TSV) and/or monolithic or 3D sequential integration on a Si substrate. The evolution, trends and challenges imposed on materials and devices are discussed for different integration technologies.
Lluis F. Marsal
Distinguished Professor and full professor at the University Rovira i Virgili, Spain.
Lluis F. Marsal
BIOGRAPHY:
Prof. Lluis F. Marsal is Distinguished Professor and full professor at the University Rovira i Virgili, Spain. Ph.D. from the University Politecnica de Cataluña, Spain, 1997. Postdoctoral researcher at the ECE, University of Waterloo, Canada (1998-1999).
In 2012, he received the URV’s RQR Award for the high quality in research and in 2014, he received the UniSA Distinguished Researcher Award, and the 2014 and 2021 ICREA Academia Awards from the Generalitat of Catalunya. Since 2019, he is the Chair of the Subcommittee for Regions/Chapters (SRC) – Regions 8 IEEE- EDS and member of the Regions & Chapters Committee and Member of the EDS Technical Committee on Photovoltaic Devices. He is a senior member of the IEEE and a member of the Distinguished Lecturer program of the EDS. He is also an Optica Fellow (formerly OSA) for his leading contributions to optoelectronic and sensing devices and photonic and optical nanostructured materials. He has been a member of advisory and technical committees in several international and national conferences and has been visiting professor at several universities and research institutions (CINVESTAV – Instituto Politécnico Nacional, Mexico, McMaster University, Canada, ICMM-CSIC, BiomaGUNE, Spain, Mawson Institute, Australia). He has co-authored more than 200 publications in international refereed journals, 2 books, 5 book chapters and 4 patents. His current research interests focus on polymer and hybrid solar cells and nanostructured materials for optoelectronic devices and low–cost technologies based on micro- and nanoporous materials for biosensing and bio-applications.
DURGA MISRA
Department of Electrical and Computer Engineering, New Jersey Institute of Technology,
DURGA MISRA
BIOGRAPHY:
Prof. Durga Misra is a Professor and the Chair of the ECE Department at New Jersey Institute of Technology. His research interests are in the areas of nanometer CMOS gate stacks and application of high-k gate dielectrics for RRAM devices. He is Fellow of IEEE and is a Distinguished Lecturer of IEEE EDS. He is, also, a Fellow of the Electrochemical Society (ECS). He received the Thomas Collinan Award from the DS&T Division and the EPD Divisional Award from ECS. He has edited more than 50 books and conference proceedings and published more than 200 technical articles in peer reviewed Journals and in International Conference proceedings. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1985 and 1988, respectively.
75th YEAR OF TRANSISTOR: EVOLUTION OF DIELECTRICS ON CMOS SCALING
Historically SiO2 was the main driver as the MOS transistor gate dielectric in CMOS technology. Once the thickness of SiO2 reached the onset of direct tunneling region (<1.5 nm) HfO2 -based high-k insulators were introduced to suppress the direct-tunneling leakage current. The evolution of dielectric science in nanoelectronics will be presented. Several applications of high-k dielectrics have emerged including ferroelectric FETs and resistive random-access memory (RRAM) devices that are being investigated for possible implementation of in-memory and artificial intelligence hardware. The electrical performance in these devices depends on the dielectric deposition process, precise selection of deposition parameters, pre-deposition surface treatments and subsequent thermal budget. The deposition of high-k on both silicon and germanium, a higher mobility channel material, will be discussed. Furthermore, the switching mechanism in transition metal oxides like HfO2 in RRAM devices, where a conducting filament path is formed due to oxygen vacancy transition/formation, will also be discussed.
MICHAEL SHUR
Dr. Michael Shur, Patricia W. and C. Sheldon Roberts Professor
Electrical, Computer, and Systems Engineering and Physics, Applied Physics, and Astronomy
MICHAEL SHUR
BIOGRAPHY:
Dr. Michael Shur is Patricia W. and C. Sheldon Roberts Professor of Solid State Electronics at Rensselaer Polytechnic Institute and co-founder of Sensor Electronics Technology, Inc., and Electronics of the Future, Inc. He is a Life Fellow of the US National Academy of Inventors, IEEE, APS, ECS, OSA, SPIE, and a Fellow of AAAS, IOP, and IET. His awards include IEEE and IET Awards, Tibbetts Award for Technology Commercialization, Senior Humboldt Research Award, RPI Research Awards, Best Paper Awards, and St. Petersburg Technical University and the University of Vilnius Honorary Doctorates. He is an IEEE EDS and Sigma Xi Distinguished Lecturer and a Foreign Member of the Lithuanian Academy of Sciences.
WIDE BAND GAP TECHNOLOGY: STATE-OF-THE-ART AND PROBLEMS TO SOLVE
Applications of wide bandgap (WBG) semiconductors, such as GaN, AlGaN, and InGaN, range from lighting and UV technology to high power, radiation hard, high temperature, terahertz (THz) electronics, and pyroelectronics. Wurtzite (hexagonal) symmetry makes these materials to be quite different from conventional cubic semiconductors. Spontaneous and piezoelectric polarization associated with the wurtzite crystal structure induces two-dimensional electron gases at AlGaN/GaN, AlInN/GaN, and AlGaN/InGaN interfaces with sheet concentrations 10 to 20 times higher than those in Si CMOS. A high current carrying capability and a high breakdown field make these materials perfect for high-power applications. Adjusting the energy gaps of AlxGa1-xN and InxGa1-xN by varying the molar fraction changes the wavelength of light they emit or absorb and enables light emitters, solar cells, and photodetectors operating from THz and infrared to deep ultraviolet range. Blue, green, and white LEDs using InGaN revolutionized smart solid-state lighting. AlGaN UV LEDs are used for water purification, fighting antibiotic-resistant bacteria and viruses, and dramatically increasing produce storage time. InN and BN have the potential to compete with the AlN/GaN family and diamond has reemerged not only as a substrate for record heat removal but also as viable THz detector material. WBG technology has many difficult problems to solve. A high dislocation density in WBG materials leads to the low efficiency of deep AlGaN UV LEDs and reliability problems of high-power devices. Non-uniformities of the electric field distribution cause a premature breakdown. Using ultrathin WBG quantum well layers and nanowires and exploring radically new device designs might alleviate or even solve these problems.
WLADEK GRABINSKI
R&D SPICE Manager at MOS-AK (EU)
WLADEK GRABINSKI
BIOGRAPHY:
Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETH Zürich, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPF Lausanne, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center,Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOS transistors for the design of RF CMOS circuits. He is currently consulting on the development of next-generation compact models for the nanoscaled technology very large scale integration (VLSI) circuit simulation. His current research interests are in high-frequency characterization, compact modeling and its Verilog-A standardization as well as device numerical simulations of MOSFETs for analog/RF low power IC applications. He is an editor of the reference modeling book Transistor Level Modeling for Analog/RF IC Design, and also authored or coauthored more than 70 papers. Wladek has established ESSDERC TPC Track3: “Device and circuit compact modeling” as well as was serving as a member of the IEEE EDS Compact Modeling Technical Committee, European representative in the ITRS Modeling and Simulation Working Group; organization committees of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ. He was a Member At Large of Swiss IEEE ExCom and mentor of the EPFL IEEE Student Branch, now. Wladek is involved in activities of the MOS-AK Association and serves as a coordinating R&D manager since 1999.
FOSS TCAD/EDA TOOLS SPICE AND VERILOG-A MODELING FLOW
Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF, Microwave, Photonics) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along the complete technology/design tool chain from nanascaled technology processes; thru the compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Application and use of these tools for advanced IC design (e.g. analog/RF, Microwave, Photonics applications) directly depends on the quality of the compact model implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the semiconductor device level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.