Jason Vidmar

Biography:

Jason Vidmar is a System Architect at Xilinx focusing on MILCOM, Satcom and Machine Learning for the Aerospace & Defense market. His professional background includes tactical and commercial communications, as well as military and commercial aerospace applications, having designed FPGA and SoC-based systems for Motorola, General Electric, Northrop Grumman and others. Mr. Vidmar has a Masters in Electrical and Computer Engineering from Illinois Institute of Technology.

Abstract:

Recent technical challenges have forced the semiconductor industry to explore options beyond the conventional “one size fits all” CPU scalar processing solution. Very large vector processing (DSP, GPU) solves some problems, but it runs into traditional scaling challenges due to inflexible, inefficient memory bandwidth usage. Traditional FPGA solutions provide programmable memory hierarchy, but the traditional hardware development flow can be a barrier to rapid development, particularly as device complexity increases. Xilinx’s latest solution combines all three elements with a new tool flow that offers a variety of different abstractions—from framework to C to RTL-level coding— into an adaptive compute acceleration platform (ACAP). This new category of devices, Xilinx’s Versal™ ACAPs, allows users to customize their own domain specific architecture (DSA) from these three programmable elements. In this session, we will highlight key aspects of the architecture, and discuss how it can enable multiple levels of heterogenous integration (including direct RF) that is crucial for breakthroughs in low-SWaP processing. Emphasis will be given to the new AI Engines, which are an array of VLIW SIMD, mixed precision vector processors, optimized for streaming DSP workloads, that deliver up to 8X silicon compute density at 50% the power consumption of traditional programmable logic solutions.