Title: Uncertainty-Aware Hardware Trojan Detection Using Multimodal Deep Learning
Presenters: Rahul Deo Vishwakarma, Founder, AI Research Club and Dheerendra Panwar, Senior Member IEEE
Abstract:
Hardware Trojan (HT) insertion is a malicious modification made to the design of a hardware component that can cause a device to malfunction, leak sensitive information, or even cause physical damage. As the semiconductor industry has adopted a fabless model, the possibility of HTs being inserted at different manufacturing stages increases, presenting a significant security threat to hardware systems. Traditional HT detection techniques such as signature-based methods that analyze the Integrated Circuit (IC) functionality, layout, and timing, are often ineffective against sophisticated HT insertion attacks, especially when the Trojans can be designed to evolve over time. Therefore, there has been a growing shift towards the use of Machine Learning (ML)-based solutions for a more effective and efficient approach to detecting HTs.
Objectives
The objective of this workshop is to provide a comprehensive understanding of the latest advancements in hardware Trojan detection, particularly focusing on the application of machine learning techniques. We aim to equip participants with the knowledge to:
- Understand the risk and impact of hardware Trojans in the semiconductor industry.
- Explore traditional and modern machine learning-based HT detection techniques.
- Implement and evaluate ML models for HT detection using conformal prediction and uncertainty quantification.
Workshop Structure
1. Introduction to Hardware Trojans
In this session, we will cover the basics of hardware Trojans, their types, and the potential risks they pose to the semiconductor industry. We will also discuss traditional HT detection techniques and their limitations.
2. Machine Learning for HT Detection
This session will focus on the application of machine learning techniques for HT detection. We will explore various ML models, including Support Vector Machine (SVM), Neural Network (NN), eXtreme Gradient Boosting (XGB), and Random Forest (RF) classifiers. Participants will learn how to extract features from the Register Transfer Level (RTL) code and train ML models for HT detection.
3. Conformal Prediction and Uncertainty Quantification
In this session, we will introduce conformal prediction as a statistical inference technique to quantify the uncertainty in HT detection. We will discuss the Mondrian conformal predictor and how it can be used to provide set predictions with guaranteed coverage. Participants will learn how to implement conformal prediction and interpret the results.
4. Practical Implementation and Case Studies
This session will provide hands-on experience in implementing ML models for HT detection. Participants will work on real-world case studies, applying the concepts learned in the previous sessions. We will also discuss the challenges and best practices in deploying ML models for HT detection in risk-sensitive domains.
Conclusion
By the end of this workshop, participants will have a solid understanding of the challenges and solutions in hardware Trojan detection using machine learning techniques. They will be equipped with practical skills to implement and evaluate ML models, ensuring robust and reliable HT detection in the semiconductor industry.
Presenter Bios:
Rahul Deo Vishwakarma, Founder, AI Research Club
Rahul Deo Vishwakarma (Senior Member, IEEE) received the Bachelor of Technology degree in computer science from the SRM Institute of Science and Technology in 2009. He completed his M.S. degree in computer science at California State University Long Beach in 2024. He worked at Hewlett Packard Enterprise (HPE), where he designed reference architectures for ConvergedSystem for SAP HANA, and Dell Technologies, he drove solutions for data protection and assisted customers in safeguarding data with data domain (deduplication-based backup storage), while leveraging machine learning across the product stack. He holds 51 granted U.S. patents in the domains of machine learning, data storage, persistent memory, DNA storage, and blockchain. His current research interests include addressing bias, explainability, and the uncertainty quantification of machine learning models.
Dheerendra (Dhee) Panwar, Senior Principal Engineer
Dheerendra (Dhee) Panwar is an accomplished professional in the realm of Internet of Things (IoT) and Machine Learning (ML), boasting a rich background of over a decade in the field. He completed his master’s degree in embedded electrical and computer systems at San Francisco State University, thereby strengthening his proficiency in this domain. Over the course of his career, he has made substantial contributions to a diverse array of IoT projects, spanning industries such as manufacturing, smart cities, retail, and energy. Having gained experience in both corporate enterprises and entrepreneurial ventures, he possesses a comprehensive grasp of the complexities of IoT/edge technologies and their pragmatic implementations.