Build Up Substrate Symposium

FINAL PROGRAM for BUSS’24: view last year’s program

The Impact of Policy on Advanced Semiconductors and Packaging Ecosystem for Aerospace and Defense

ADVANCE PROGRAM
Thursday, May 8, 2025
Time	Speaker	Title/Abstract
Keynote Addresses
	Sai Boyapati, Director of Technology Development, AMD Advanced Packaging	Advanced Packaging Substrate Technologies for Power Efficient AI Products — : This talk outlines the AMD advancements in power-efficient AI through advanced packaging technologies. It highlights AMD’s end-to-end portfolio, including processors, GPUs, and accelerators designed for various applications from endpoints to cloud computing. Then it discusses the challenges of traditional Moore’s Law scaling, increasing costs, and thermal impacts … (more)
	E. Jan Vardaman, President and Founder, TechSearch International, Inc.	Substrate Market Outlook — Substrates are essential for IC packagers. For high performance applications such as AI, server CPU, and network switches build-up substrates with multiple layers are required. Automotive requires substrates that meet special reliability requirements. Many of high-performance packages use a silicon or redistribution layer (RDL) … (more)
Session 1: Substrate Challenges for Chiplet Integration Chair: Rozalia Beica, Rapidus
	Venkata Mokkapati, Director, Business Development & Application Engineering, AT&S AG	Addressing New Challenges with Conventional Organic Substrates — The industry has been looking for alternative solutions to address substrate challenges, especially integration on larger packages which are even beyond current Jedec standards. There are several technologies that have been proposed which could solve these problems, organic solutions for example … (more)
	Shingo Hayashibe, Shinko Electric America, Inc.	Large Form Factor Chiplet Package using an Organic Interposer for Chip-last Assembly — Interposers that integrate multiple semiconductor chips are rapidly becoming larger. SHINKO’s i-THOP, an organic interposer with 2.3D structure, using semiconductor thin-film technology and Shinko’s assembly processes is one solution for these large size interposers … (more)
	Satoru Kuramochi, Research Fellow, Fine Packaging Division, Dai Nippon Printing Co. (DNP)	Large Scale Glass Substrate for High Performance Computing Application — As the industry moves toward High Performance Computing (HPC) for huge data transmission with low power consumption. The requirements for PKG structure have become more challenging. The major engineering requirements for HPC application are high-density, high-speed data transmission … (more)
	Vern Stygar, AGC	Glass Compositions for Data Centers, AI, and Quantum Computing — The use of glass as a core material for electronic and photonic packaging substrates is being considered due to its rigidity, flatness, and dimensional stability for advanced packaging such as chiplet packaging requiring large format and high-density interconnection. This presentation will provide an overview of glass material technology, processing technology and the need for reliability testing for glass core substrates … (more)
Session 2: Materials for Substrates Chair: Annette Teng, NY Creates
	Shiro Tatsumi, Ajinomoto	Advanced Insulation Material for High Performance Semiconductor Packages — Printed circuit boards such as multi-layer printed wiring boards and flexible printed wiring boards are used for a wide variety of electronic devices. Ajinomoto Build-up Film®(ABF) has been widely utilized for a variety of package structures due to its outstanding insulation reliability, good resin flow, thickness uniformity and Semi-Additive Process (SAP) compatibility for fine line and space formation. Low coefficient of thermal expansion (CTE) … (more)
	Yuya Suzuki, Taiyo America	Dry-film Solder Resist Materials for High Density IC Substrates — The demand for high-density integrated circuit (IC) substrates is driving advancements in material technologies to meet the increasing complexity and performance requirements of high-performance electronics. Solder resist (SR) materials play a critical role in IC substrate applications by providing insulation and protecting circuit patterns… (more)
	Hikaru Mizuno, JSR Micro	Advanced Photo-imageable Dielectric Film Enabling Sub-5-micron Patterning for Next Generation Build-up Layer — As novel electronic products become dramatically smaller and more highly functionalized, semiconductor packaging structures are also required to become smaller, thinner and more complicated. Based on these market trends, the IC substrate has become one of the most important components in packaging. Next-generation build-up layer patterning materials for IC substrates are required to meet the demands of ultra-fine via patterning… (more)
	Masa Fukui, Resonac America, Inc.	Substrate Materials for Advanced Packaging — The development of advanced packaging technology has been accelerated, such as for 2.5D packaging and chiplet design. Advanced packaging requires HSIO, high density interconnection and large form factor. This motivation for future packaging is the driving force behind the development of substrate materials to meet the challenges. In this perspective, glass substrates are considered as the future generation substrate … (more)
Session 3: Emerging Substrate Technologies Chair: Steven Verhaverbeke, Applied Materials
	Jason Conrad, Arizona State University, and Craig Bishop, Chief Technology Officer, Deca Technologies	SHIELD USA: Leap-ahead Organic Substrate Technology — The CHIPS Act renewed a domestic focus on semiconductor technology, including advanced packaging that is critical for chiplets and future scaling. Under the National Advanced Packaging Manufacturing Program (NAPMP), ASU is leading the Substrate-based Heterogeneous Integration Enabling Leadership Demonstration for the USA (SHIELD USA) program … (more)
	Steven Verhaverbeke, Applied Materials	Wafer-Level Si Core Substrates – Third Leg of the NAPMP Substrates Program — The rise of chiplet and 2.5D packaging has been driven by the increasing demands for higher performance, scalability, and power efficiency in modern semiconductor design. As Moore’s Law slows, traditional monolithic scaling becomes less viable due to cost and yield challenges. 2.5D packaging, which utilizes an interposer to connect multiple chiplets… (more)
	Sung Jin Kim, Ph.D., CTO, Absolics	(to be provided) — (to be provided) … (more)
Panel: Technology Development R&D Centers of Excellence		Moderators: Jan Vardaman, TechSearch International; Yoji Nakajima, TEL ASU, iNEMI, UCLA, GaTech (tentative)
Friday, May 9, 2025
Keynote Addresses
	Keynote Talk: Omar Bchir, Qualcomm	Next Generation Organic Substrate Technology: How Will it Synergize with 2.5D? — As chiplet packaging proliferates, a reduction in die interconnect pitch and concomitant increase in escape routing density must be enabled to meet performance and cost targets. The traditional 2D solution (die on organic substrate) has limitations related to pitch and escape routing capability, which have promoted a shift to 2.5D technology … (more)
Session 4: Panel Equipment and Technologies for Substrates Chair: Kuldip Johal, MKS
	Niranjan Khasgiwale, Digital Lithography BU, Applied Materials	Addressing Advanced Packaging Scaling and Yield Challenges with Mask-less Lithography — The AI race is accelerating move towards 3D heterogeneous integrated architectures and density scaling in substrate manufacturing. The extreme power-hungry workloads in data centers necessitates transition to larger chip modules, more build-up layers in substrates and embedding devices … (more)
	Yoshihiro Inoue, Nikko-Materials	The Latest Vacuum Lamination Challenges and Technology Development — This talk will cover essentials of the vacuum lamination process for the lamination of film materials, introducing NM’s widely applicable vacuum laminator with lamination process towards uneven surface … (more)
	Martin Orrick, MKS Instruments Inc	Small Via Formation in Next Generation IC Substrates — Across a wide field of IC Substrate applications, from Mobile devices to AI Servers, the common themes of increasing complexities, package size, increasing routing densities, smaller lines and spaces, and correspondingly smaller laser drilled vias are prevalent … (more)
Session 5: Design Integrations Chair: Farhang Yazdani, Broadpak
	Dr. Debendra Das Sharma, Data Platforms and Artificial Intelligence Group, Intel Fellow	UCIe 2.0: Open Chiplet Innovation Continues with Vertical and Planar Connectivity — High-performance workloads demand on-package integration of heterogeneous processing units, on-package memory, and communication infrastructure such as co-packaged optics to meet the demands of the supercomputing landscape. On-package interconnects are a critical component to deliver the power-efficient performance … (more)
	Timothy Lee, Boeing	The Impact of Policy on Advanced Semiconductors and Packaging Ecosystem for Aerospace and Defense — (to be provided) … (more)
	Dr. John Damoulakis, Sr. Director – Advanced Technology Programs, Cadence Design Systems	Complexity Handling of Integrated Circuits Design Using AI-based EDA Technology with Smart Substrates — The advent of microelectronics technology evolution has from one hand created numerous market opportunities for applications in high-performance-computing (e.g., data centers) and ultra-low-power (e.g., biomedical, automotive, etc.) electronics that were not possible before, but on the other hand has created substantial complexity in the design … (more)
Session 6: Metrology Chair: Yoji Nakajima, TEL
	Dr Robert Bishop, Beltronics	Advanced Metrology for High Density Substrates — High-density substrates are being fabricated for advanced packaging with increasingly fine features, with some roadmaps calling for 2µm lines and spaces. In order to manufacture these build-up substrates it is critical to use inline metrology … (more)
	Monita Pau, Onto Innovation	Accelerating Advanced IC Substrate Development with Versatile Process Control Solutions — (to be provided) … (more)
	Barton A. Katz, President & Chief Commercial Officer, Nanospan Technologies	Advanced Inspection and Metrology for Glass Panel Processing — Glass Core Panels with dimensions of 510mm x 515mm are of high interest to the industry in terms of advanced packaging applications. Specifically, panel edges have been highlighted as areas of vulnerability relative to cracks and related debris … (more)
Panel: What is Needed to Reduce the Gap Between US and Overseas Substrate Manufacturing?		Moderators: Venky Sundaram, 3D System Scaling; Kuldip Johal, MKS instruments Calumet, TTM, Sanmina, Shinko, Green Source Fab, AT&S (tentative)