IEEE CASS Seasonal School 2021 on Domain Specific Accelerator Architectures
The Seasonal school will be held on 20-27 September 2021 in virtual Mode and will be featuring top speakers with expertise in building hardware accelerators for diverse applications such as LDPC based advanced error correction, inference and training of deep neural networks.
The IEEE CASS Chapters of UAE, Lebanon, Egypt, Columbia and Hyderabad present the IEEE CASS Seasonal School on “Domain Specific Accelerator Architectures”.
The seasonal school of this year will focus about Domain Specific Accelerator Architectures. A domain-specific accelerator is a hardware computer engine tailored to a certain application domain. Graphics, error correction, deep learning, simulation, bioinformatics, image processing, and a variety of other applications have all been aided by accelerators.
Industry implementations and the IEEE standards group studies have shown that TAMU LDPC has up to 75% savings in area and power over other LDPC designs and two orders of improvements over algebraic-coded implementations. TAMU LDPC is the most advanced Low-Density Parity-Check (LDPC) code technology, originally developed and patented by Texas A&M University (TAMU) and is now currently used in high-volume storage and communication industry products. Dr. Kiran Gunnam, the primary inventor of TAMU LDPC and now a Distinguished Engineer at Western Digital Research, will be delivering an Opening Distinguished 2-part tutorial on “Domain Specific Accelerator (DSA) architectures for Signal Processing, Communications and Machine Learning” and “LDPC-based Advanced Error Correction Coding Architectures”.
Also the program features the following additional talks from the subject experts:
Day 2: Efficient Hardware Implementations for Accelerating DNN-based Inference, (Dr. Partha Maji, Principal Research Scientist, ARM, UK)
Day 3: The Groq Tensor Streaming Processor (TSP) and the Value of Deterministic Instruction Execution, (Mr. Andrew Ling, Director of Software. Groq, Silicon Valley)
Day 4: Domain Specific Accelerator (DSA) architectures for efficient execution of sparse workloads on FPGA platforms, (Dr. Abhishek Jain, Adaptive Platform Architect, Xilinx, Silicon Valley)
Day 5: Hitchhikers Guide to Wafer-Scale AI, (Mr. Michael James, Chief Scientist, Cerebras, Silicon Valley)
The 5-day program includes 3 hours of lecture followed by a Q&A session every day. The program and free registration information can be found at https://attend.ieee.org/cass-ss . The Organizing Committee includes Chairs of the five IEEE CASS Chapters: Dr. Vinod Pangracious, Dr. Abdallah Kassem, Dr. Ahmad Madian ,Dr. Mohammed Arifuddin Sohel and Dr. Faruk Fonthal Rico. Prof. Francisco García, Universidad Nebrija will be the editor for the e-book of the program.