Distinguished Engineer - Machine Learning & Computer Vision, Western Digital, USA.

Dr. Gunnam is also a key contributor to the precise localization and navigation technology commercialized for autonomous aerial refueling and space docking applications. His recent patent pending inventions on low-complexity simultaneous localization and mapping (SLAM) and 3D convolutional neural network (CNN) for object detection, tracking and classification are being commercialized for LiDAR+camera based perception for autonomous driving and robotic systems.

Dr. Gunnam received his MSEE and PhD in Computer Engineering from Texas A&M University, College Station. He is world-renowned for balance between strong analytical ability and pragmatic insight into implementation of advanced technology. He served as IEEE Distinguished Speaker and Plenary Speaker for 25+ events and international conferences and more than 3000 attendees in the USA, Canada and Asia benefited from his talks.

Mr. Andrew Ling

Director of Software. Groq, Silicon Valley

Andrew Ling received his Ph.D. from the University of Toronto in 2009. After that, he spent most of his time at Altera, which was later acquired by Intel. His primary focus at Altera/Intel was the development of the OpenCL compiler and later on, moved into CNN acceleration for FPGAs. He now leads the Groq Canada Design Centre, where they are focused on developing scalable ML software and compiler tools for the Groq TSP.

Adaptive Platform Architect, Xilinx, Silicon Valley

Abhishek Jain is a staff architect at Xilinx responsible for the design, modelling, simulation/emulation and evaluation of domain-specific compute and interconnect architectures. After receiving his PhD in Computer Engineering from NTU Singapore in 2016, Abhishek explored near memory accelerators and system-level emulation techniques while working as a Postdoc at Lawrence Livermore National Lab. During his Ph.D., Abhishek developed techniques for building high-performance on-chip interconnect and processor array overlays for dataflow acceleration on FPGAs. His research interests include reconfigurable systems, on-chip networks, domain-specific accelerators, and system-level interconnect architectures for FPGA/SoC platforms.

Dr. Partha Maji

Principal Research Scientist, ARM

Dr Partha Maji is currently a Principal Research Scientist at Arm’s Machine Learning Research Lab based in Cambridge, where he drives the core research in the efficient implementation of probabilistic machine learning on resource-constrained devices. Prior to this, he worked as a Staff SoC Design Engineer at Broadcom Ltd. where he led various front-end and back-end design and implementation activities. Partha started his career in the semiconductor industry as a Micro-architecture design engineer in the Processor Division group at Arm. He also spent in the software industry for a while before embarking on chip design. He has extensive experience with the end-to-end chip design process starting from microarchitecture-level design to physical design through multiple tape-outs of low-power chips at 65/40/28/22nm deep-submicron CMOS process technology. His current research interests lie in multiple disciplines that bridge the topics of machine learning, mobile/embedded systems, computer architecture and hardware implementation. Partha has received several excellence awards from the industry including a Mentor Graphics prize for outstanding achievement in the master’s degree. Partha also received multiple accolades for his research in on-chip interconnect including an award from Epson Europe and the IET, UK. He was also recognized by the European Neural Network Society for his high-quality contribution to machine learning research. Partha was a recipient of the prestigious UK Chevening scholarship. He received a PhD in Computer Science from the University of Cambridge and an MSc in System-on-Chip design from the University of Edinburgh.

Michael James

Chief Architect, Cerebras Systems, Silicon Valley

Michael is Founder and Chief Architect of Advanced Technologies at Cerebras, the company that created the world’s largest and most powerful computer processor. Michael leads the effort to reimagine the algorithmic building blocks for the next generation of AI technologies. Prior to Cerebras, Michael was a Fellow at AMD, where he pioneered a technique of adaptive and self-healing circuits based on cellular automata that was applied toward distributed fault tolerant machines. Michael focuses his career on exploration at the intersection of natural phenomena, mathematics, and engineered machines. Michael has degrees in Molecular Neurobiology, Computer Science and Mathematics from UC Berkeley.