Accelerating AI with Chiplet Technology
Tony Chan Carusone Alphawave & University of Toronto
Abstract:
Chiplet technology is revolutionizing our digital infrastructure. The reductions in cost, time-to-market, and power consumption of chiplet-based solutions are compelling, particularly for AI hardware. Custom silicon for AI significantly benefits from the chiplet approach, which allows for the integration of dense logic, memory, and high-speed connectivity. Chiplets provide the flexibility to create systems-in-package that balance cost, power, and performance for specific workloads without reinventing the wheel for each new design. As chiplet adoption grows, it drives increased bandwidth requirements within packages and across die-to-die interfaces. Scaling AI performance requires low-latency inter-die communication and lots of high-speed optical connectivity.
Bio:
Dr. Tony Chan Carusone has taught and researched integrated circuits and systems for high-speed connectivity in industry and academia for over 20 years. He has been the Chief Technology Officer of Alphawave Semi since 2022 and a faculty member at the University of Toronto since completing his Ph.D. there in 2002. He has well over 100 publications, including 11 award-winning best papers at leading conferences for work on chip-to-chip and optical communication, analog-to-digital conversion, and precise clock generation. He also co-authored the latest editions of the classic textbooks “Analog Integrated Circuit Design” and “Microelectronic Circuits,” the best-selling engineering textbook of all time. Tony has also been a consultant to the semiconductor industry for over 20 years, working with both startups and some of the largest technology companies in the world. He is a Fellow of the IEEE.
Advanced Chiplet Package Signal Integrity for Future Data Center and AI
Dean Gonzales AMD
Abstract:
Advanced Packaging Chiplet technologies have enabled large-scale deployment of heterogenous compute to address the disparate demands of the mega data center and the voraciously growing machine intelligence market. These advanced server CPU and GPU based systems require very high chip-to-chip IO connectivity and memory bandwidths with strict power, area, and latency optimization for scaling up and scaling out of rack-based systems. While dense integration brings together new capacity to solve the industry’s most pressing problems, these Chiplets and high-power systems have abundant mechanical complexity and sensitivity to manufacturing variation. Even minor imperfections can have a profound impact on signal-to-noise margin at large scale system production. This discussion is an overview of the unique signal and power integrity design challenges for building these advanced Chiplet based products and systems with low defect rate requirements.
Bio:
Dean Gonzales is an AMD Fellow with three decades of experience working on the design of silicon, advanced packaging technology, and computer
systems. His signal integrity focus helps drive AMD pathfinding to improve power, area, and performance of silicon interconnects. Dean brings to this talk a passion for I0 electrical standardization and compliant channel design and modeling methodologies.