Tutorials

Tutorial Program (Preliminary)

Signal and Power Integrity Analysis Using LIM – Recent Advances

Jose Schutt-Aine University of Illinois Urbana-Champaign

 

Packaging Technology for Next Generation mmWave Commmunications: Scalable Heterogeneous AiP Modules and the Future Role of Chiplets

Atom Watanabe IBM Research

Abstract: This talk cover the emerging packaging technology trends for mmWave communications with a focus on the design and integration methodologies for scalable phased array antenna modules. The presentation will first describe a heterogeneous integration strategy used to facilitate the effective integration of various active ICs, passive components, and decoupling capacitors into a substrate to form a 5G scalable phased array antenna module. The talk will also discuss the anticipated advantages of adopting a chiplet-based approach for digital baseband processing enabling the implementation of full end-to-end antennas-to-AI systems for the next generation of energy-efficient and adaptive mmWave networks.

Bio: Atom O. Watanabe is a Research Scientist who currently works at the IBM T. J. Watson Research Center as an IC packaging architect for advanced packaging and heterogeneous chiplet integrations. His current research interests and expertise include modeling and design, signal/power integrity analysis, and hardware characterization for millimeter-wave packages, co-packaged optics, high-performance computations, and quantum computers.
Dr. Watanabe’s contributions to the field include over 40 publications in renowned journals such as Applied Physics Letters, IEEE Transactions on Components, Packaging, and Manufacturing Technology, IEEE Transactions on Microwave Theory and Techniques, and IEEE Transactions Electromagnetic Compatibility, as well as numerous presentations at top-tier conferences like the Electronic Components and Technology Conference (ECTC) and Chiplet Summit. Furthermore, Dr. Watanabe has received multiple paper awards in recognition of his work. He has been serving on technical program committees for IEEE Microwave Theory and Technology Society and Chiplet Summit. He obtained a PhD in electrical and computer engineering from the Georgia Institute of Technology.

Title TBD

Vaishnav Srinivas Qualcomm

Madhavan Swaminathan Pennsylvania State University

Chiplet Design and Heterogeneous Integration Packaging

John H. Lau Unimicron Technology Corporation

Abstract:

Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.

    • System-on-Chip (SoC)
    • Why Chiplet Design?
    • Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split
      • Chip partition and Heterogeneous Integration
      • Chip split and Heterogeneous Integration
      • Advantages and Disadvantages
    • Communication between Chiplets (e.g., Bridges)
      • Bridge Embedded in Build-up Package Substrate
      • Bridge Embedded in Fan-Out EMC with RDLs
      • UCIe
      • Hybrid Bonding Bridge
    • Chiplet Design and Heterogeneous Integration Packaging – Multiple System and Heterogeneous Integration
      • Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)
      • Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration)
      • Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)
      • Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration)
      • Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)
    • Advanced Packaging Driving by Artificial Intelligent
    • Summary
    • Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging
    • Trends in Chiplet Design and Heterogeneous Integration Packaging

Bio: John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging has published more than 533 peer-reviewed papers (380 are the principal investigator), 50 issued and pending US patents (32 are the principal inventor), and 23 textbooks (all are the first author) such as Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023) and Flip Chip, Hybrid Bonding, Fan-In, and fan-Out Technology (Springer, 2024). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.