Tutorials - EPEPS 2024 - 33rd IEEE Conference on Electrical Performance of Electronic Packaging and Systems

Tutorial Program (Preliminary)

Signal and Power Integrity Analysis Using LIM – Recent Advances

Jose Schutt-Aine University of Illinois Urbana-Champaign

Abstract: With the increase in complexity and size of modern circuits, signal integrity has become an important aspect in the the study of the performance of electronic systems. Circuit designers are constantly in need of robust and efficient circuit simulation methods that can capture complex electromagnetic behaviors of networks and devices in fast turnaround time. As a result, there is a constant need for and push toward faster and more accurate circuit simulation techniques. The latency insertion method (LIM) has emerged as an approach of choice for performing fast simulations of very large circuits. By exploiting latencies in a circuit, LIM implements an algorithm that achieves linear numerical complexity. This results in a computationally efficient algorithm that is able to simulate large circuits significantly faster than traditional matrix inversion-based methods used in simulators such as SPICE.

In this tutorial we review the fundamentals of the latency insertion method and explore applications related to new technologies. Recent advances, several examples and case studies related to signal/power integrity and large circuits will be presented.

Bio: José E. Schutt-Ainé is with the faculty in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His research interests are on signal integrity for high-speed digital and high-frequency applications. Dr. Schutt-Ainé is an IEEE Fellow, EPS Distinguished Lecturer, and served as Co-Editor-in-Chief of the IEEE Transactions on Components, Packaging and Manufacturing Technology (T-CPMT) from 2007 to 2018. He is currently chairing the Co-design chapter of the IEEE-EPS Co-Design Chapter of the Heterogeneous Integration Roadmap.

Packaging Technology for Next Generation mmWave Commmunications: Scalable Heterogeneous AiP Modules and the Future Role of Chiplets

Atom Watanabe IBM Research

Abstract: This talk cover the emerging packaging technology trends for mmWave communications with a focus on the design and integration methodologies for scalable phased array antenna modules. The presentation will first describe a heterogeneous integration strategy used to facilitate the effective integration of various active ICs, passive components, and decoupling capacitors into a substrate to form a 5G scalable phased array antenna module. The talk will also discuss the anticipated advantages of adopting a chiplet-based approach for digital baseband processing enabling the implementation of full end-to-end antennas-to-AI systems for the next generation of energy-efficient and adaptive mmWave networks.

Bio: Atom O. Watanabe is a Research Scientist who currently works at the IBM T. J. Watson Research Center as an IC packaging architect for advanced packaging and heterogeneous chiplet integrations. His current research interests and expertise include modeling and design, signal/power integrity analysis, and hardware characterization for millimeter-wave packages, co-packaged optics, high-performance computations, and quantum computers.
Dr. Watanabe’s contributions to the field include over 40 publications in renowned journals such as Applied Physics Letters, IEEE Transactions on Components, Packaging, and Manufacturing Technology, IEEE Transactions on Microwave Theory and Techniques, and IEEE Transactions Electromagnetic Compatibility, as well as numerous presentations at top-tier conferences like the Electronic Components and Technology Conference (ECTC) and Chiplet Summit. Furthermore, Dr. Watanabe has received multiple paper awards in recognition of his work. He has been serving on technical program committees for IEEE Microwave Theory and Technology Society and Chiplet Summit. He obtained a PhD in electrical and computer engineering from the Georgia Institute of Technology.

Abstraction for Heterogeneous Integration

Vaishnav Srinivas Qualcomm

Madhavan Swaminathan Pennsylvania State University

Chiplet Design and Heterogeneous Integration Packaging

John H. Lau Unimicron Technology Corporation

Abstract:

Chiplet is a chip design method and heterogeneous integration is a chip packaging method. Chiplet design and heterogeneous integration packaging have been generated lots of tractions lately. For the next few years, we will see more implementations of a higher level of chiplet designs and heterogeneous integration packaging, whether it is for cost, time-to-market, performance, form factor, or power consumption. In this lecture, the following topics will be covered.

- System-on-Chip (SoC)
- Why Chiplet Design?
- Chiplet Design and Heterogeneous Integration Packaging – Chip Partition and Chip Split
  - Chip partition and Heterogeneous Integration
  - Chip split and Heterogeneous Integration
  - Advantages and Disadvantages
- Communication between Chiplets (e.g., Bridges)
  - Bridge Embedded in Build-up Package Substrate
  - Bridge Embedded in Fan-Out EMC with RDLs
  - UCIe
  - Hybrid Bonding Bridge
- Chiplet Design and Heterogeneous Integration Packaging – Multiple System and Heterogeneous Integration
  - Multiple System and Heterogeneous Integration with Package Substrate (2D IC Integration)
  - Multiple System and Heterogeneous Integration with Thin Film layer on the Package Substrate (2.1D IC Integration)
  - Multiple System and Heterogeneous Integration with TSV-less (Organic) Interposer (2.3D IC Integration)
  - Multiple System and Heterogeneous Integration with Passive TSV-Interposer (2.5D IC Integration)
  - Multiple System and Heterogeneous Integration with Active TSV-Interposer (3D IC Integration)
- Advanced Packaging Driving by Artificial Intelligent
- Summary
- Potential R&D Topics in Chiplet Design and Heterogeneous Integration Packaging
- Trends in Chiplet Design and Heterogeneous Integration Packaging

Bio: John H Lau, with more than 40 years of R&D and manufacturing experience in semiconductor packaging has published more than 533 peer-reviewed papers (380 are the principal investigator), 50 issued and pending US patents (32 are the principal inventor), and 23 textbooks (all are the first author) such as Chiplet Design and Heterogeneous Integration Packaging (Springer, 2023) and Flip Chip, Hybrid Bonding, Fan-In, and fan-Out Technology (Springer, 2024). John is an elected IEEE fellow, IMAPS Fellow, and ASME Fellow and has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.

Superconducting Circuit Quantum Computers: Fundamental Concepts and Scaling Challenges

Thomas Roth Purdue University

Abstract:

Superconducting circuit devices are one of the most mature hardware platforms for developing quantum computers, but significant engineering advances are needed for them to reach their revolutionary potential in practical applications. One primary challenge is to scale the number of quantum bits (qubits) in devices by orders of magnitude while continuing to improve key performance metrics. In this tutorial, we will introduce the fundamental concepts of how superconducting circuit quantum computers operate assuming no prior knowledge in quantum mechanics. We will discuss the key aspects of the primary qubit type currently being used, as well as how microwave fields and electronic biases are used to control and measure qubit states. We will then briefly discuss current hardware and computational modeling efforts underway that are working to address the scaling challenges of these systems. We will conclude with comments on directions for future work and the roles the electronics packaging community can play in making these revolutionary technologies a reality.

Bio:

Thomas E. Roth is an Assistant Professor in the Elmore Family School of Electrical and Computer Engineering. He received all his degrees in electrical and computer engineering, with the B.S. degrees from Missouri University of Science and Technology and the M.S. and Ph.D degrees from the University of Illinois at Urbana-Champaign. Prior to joining Purdue, he was a Senior Member of the Technical Staff at Sandia National Laboratories in the Radar Electromagnetics & Sensor Technologies department where he was named a 2019 Up & Coming Innovator. He is the recipient of Young Scientist Awards at the 2023 Photonics & Electromagnetics Research Symposium and the URSI International Symposium on Electromagnetic Theory 2023 (1st place), a recipient of the 2023 IEEE Ulrich L. Rohde Innovative Conference Paper Award on Computational Techniques in Electromagnetics, as well as the 2023 Ruth and Joel Spira Outstanding Teacher Award at Purdue University. His research focuses on multiscale and multiphysics computational electromagnetics techniques, particularly for analyzing and designing quantum information processing devices.

Practical aspects of FD-TDR co-modification for high-speed structures’ matching and what-if simulations

Pavel Vilner Nvidia Networking Signal Integrity Group

Abstract:

Time Domain Reflectometry (TDR) is a widely used technique in design of high-speed (HS) serial digital channels. It is frequently employed as a post-processing step for VNA measurements and Frequency Domain (FD) electromagnetic simulations’ results to assess the localized channel impedance as the assumed propagating signal sees it. The TDR well-known connection to the channel’s topology and design features makes it useful in identifying changes needed to achieve the desired system performance. Thus, when the TDR or FD results are not satisfactory, two questions often arise – (1) what the FD data will look like if some TDR feature is changed, and (2) what TDR feature needs to be changed to modify an undesired aspect of the FD data. Answering those questions requires co-modifying the TDR result and its respective FD representation.

While the Fourier theory underpinning FD-TDR co-modification is well known, this presentation deals with finer practical points needed to implement it. Extrapolation of the original FD data to achieve the desired bandwidth, application of the modification window functions, considerations in modifying the complex-valued FD data and influence of computational precision are discussed. Examples in MATLAB are given, and their usefulness in improving their respective HS structures’ topology is showcased.

Bio:

Pavel Vilner is a Senior Manager in the Nvidia Networking Signal Integrity Group (Toronto office), working on connectivity solutions for Nvidia NVLink, InfiniBand and Ethernet products. His interests include high-speed serial links’ performance analysis, modeling and measurements of passive structures in high-speed serial interconnects and computational electromagnetics. He graduated from the Technion (Israel Institute of Technology) in 2019 with M.Sc. in Electrical Engineering and B.Sc. in Physics.