Call for Papers

The organizing committee of the IEEE DMC promises that this conference will be an excellent opportunity for networking, technical learning, and cross pollination of ideas. We will give our best to make this conference a watermark moment for the power electronics society.

Conference topics of interest include, but are not limited to:


  • Design Space Exploration
  • Layout Synthesis
  • Automatic Testing and Verification Techniques
  • New Device Models
  • Model Order Reduction
  • Optimization Techniques
  • Hardware and Power in the Loop
  • Digital Twin
  • Magnetics Design Optimization
  • Considerations of Lifetime prediction


  • Firmware compromise detection and integrity verification
  • Cyber‐physical attacks and approaches for hardware hardening
  • Integration of hardware‐ and software‐based hardening solutions
  • Seamless Transition to communication-free control of multi converter systems
  • Device-level and system-level cybersecurity challenges and solutions
  • Cyber-Physical Security of Electric Vehicles and Electric Vehicle Charging Infrastructure
  • Resilient power electronic control
  • Cyber-Physical Security of Solid State Transformers
  • Steady State and Dynamic Analysis of Power Electronic Systems under Cyber Attacks
  • Artificial Intelligence based Cyber-attack detection and classification methods
  • Testbeds for investigation of cyber-security incidents and mitigation schemes
  • Digital Twins of power electronic systems for surrogate model based detection of Cyber Incidents


  • Artificial Intelligence in the power electronics control
  • Artificial Intelligence for automated circuit synthesis
  • Estimation and maintenance of power electronics systems
  • Condition monitoring, Anomaly Detection and Fault Diagnosis
  • Artificial Intelligence for the design of power electronics components and systems
  • AI methods (Machine learning, Neural network, fuzzy logic…) and Applications in Power Electronics

Digest Submission: Prospective authors are requested to submit a single column, single spaced digest no longer than five (5) pages summarizing the proposed paper. The digest will address the problem, the major results and its contribution in comparison with previous research works. It should include key equations, figures, tables, and references as appropriate, but no author names or affiliations. Digests not conforming to these requirements will be rejected without review. All digests will go through a double-blind peer review process to ensure a confidential and fair review. The papers presented at the conference will be included in the IEEE Xplore Digital Library. Please refer to the conference website for a detailed list of technical topics and the digest submission method.


The IEEE DMC Organizing Committee would like to thank you for your trust, participation, enthusiasm and overall energy that helped to drive us to make this first step towards a prestigious conference of strategic importance for the Power Electronics Society.

To pave the way to the conference a series of web seminars is offered by PELS. Each month a webinar presenting a different topic from the field of design methodologies until we meet at the DMC 2021 in Bath.