Reliability Challenges in Advanced Packaging
Subramanian S. Iyer, Center for Heterogeneous Integration and Performance Scaling, Samueli School of Engineering, University of California, Los Angeles
ABSTRACT: As CMOS scaling saturates, more and more of the onus of electronics system performance scaling has fallen on packaging, giving rise to the term “advanced” packaging and heterogeneous integration. The driving force for advanced packaging is similar to CMOS scaling: lower system cost, smaller footprints and increased performance. The method of achieving this is also similar – shrink the package and the board and increase the inter-die bandwidth and reduce inter-die latency and energy per bit transmitted. Traditional packaging has been notorious for dominating the failure Pareto distribution. This stems from the complexity of packaging: solder and related brittle intermetallics, the mixing of silicon and inorganics with organic materials with their vastly different thermal and mechanical properties including coefficients of thermal expansion, and connector technology coupled with the use of larger and larger dies. Advanced packaging tends to use silicon-like processing and can be potentially less susceptible to these failure modes. However, we do expect to see different failure modes creep in. In this talk we will look at this problem from the perspective of three-dimensional integration, interposer technology, the silicon interconnect fabric as well as fan-out wafer-level packaging and flexible hybrid electronics. We argue that more integration and more intimate integration with minimal possibility for rework will make increasing use of system reliability concepts such as redundancy, smart thermal management, intelligent routing and a high degree of fault tolerance to achieve overall greater system reliability.
Subramanian S. Iyer (Subu) is Distinguished Professor and holds the Charles P. Reames Endowed Chair in the Electrical Engineering Department and a joint appointment in the Materials Science and Engineering Department at the University of California at Los Angeles. He is Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS). Prior to that he was an IBM Fellow. His key technical contributions have been the development of the world’s first SiGe base HBT, Salicide, electrical fuses, embedded DRAM and 45nm technology node used to make the first generation of truly low-power portable devices as well as the first commercial interposer and 3D integrated products. He also was among the first to commercialize bonded SOI for CMOS applications through a start-up called SiBond LLC. More recently, he has been exploring new packaging paradigms and device innovations that may enable wafer-scale architectures, in-memory analog compute and medical engineering applications. He has published over 300 papers and holds over 75 patents. He has received several outstanding technical achievements and corporate awards at IBM. He is an IEEE Fellow, an APS Fellow and a Distinguished Lecturer of the IEEE EDS and EPS and a member of the Board of Governors of IEEE EPS. He is also a Fellow of the National Academy of Inventors. He is a Distinguished Alumnus of IIT Bombay and received the IEEE Daniel Noble Medal for emerging technologies in 2012.
Emerging Reliability Challenges: Solutions from Architecture to Layout for Large SoCs and 3DICs,
Norman Chang, Ansys Fellow and Chief Technologist at Semiconductor BU, ANSYS, Inc.
ABSTRACT: With the emergence of complex 3DIC designs for AI/5G/HPC and Silicon Photonics applications, a comprehensive reliability solution is needed from architecture to layout stages of the design. Reliability checks cannot just be addressed in the latter stages of design. They must be taken into consideration early on due to the ramifications of logic partitioning, TSV placement, and logic/memory chip proximity under different workloads. Reliability analysis spans multiple levels of design, from devices to cells, blocks/partitions, dies, interposer, package, and board; each impacts the others. Specifically, thermal and thermal-induced stress is an important consideration for 3DIC designs due to heat dissipation concerns, Joule heating, and coupling effects. A fast ML-augmented hierarchical thermal simulation is necessary to enable accurate thermal analysis at the scale of 3DIC designs. Other applications include thermal sensor placement optimization, thermal run-away checks, and DVFS strategy. In this talk we will address the emerging challenges in the reliability space using novel applications of proven simulation technologies. An application of running thermal analysis on a 3DIC design with interposer-based architecture will also be demonstrated.
Bio: Norman Chang co-founded Apache Design Solutions in February 2001 and currently serves as Ansys Fellow and Chief Technologist at Semiconductor BU, ANSYS, Inc. Dr. Chang received his Ph.D. in Electrical Engineering and Computer Sciences from University of California, Berkeley. He holds eighteen patents and has authored over 50 technical papers. He is currently on the committee for ESDA-EDA and Si2 AI/ML TAB.
Silicon Photonics: State-Of-The-Art, Challenges, and Future Requirements
Vipul Patel, Senior Technologist, Cisco Systems Inc.
ABSTRACT: Silicon Photonics is an emerging technology that is bringing a paradigm shift in the field of fiber-optic communications. Silicon Photonics leverages mature CMOS wafer fabrication and packaging infrastructures to deliver high bandwidth, low power transceivers. Realizing the potential of this technology, Cisco has invested significantly in this area by acquiring Lightwire and Luxtera and has announced intent to acquire Acacia. Even though the current focus of the industry is to develop products for the pluggable market, it is generally accepted that Silicon Photonics will play a key role in the next generation of optics that is needed for co-packaging with ASICs. In this talk, trends and opportunities in Silicon Photonics for networking applications will be reviewed with emphasis on standardization that is needed for efficient supply chain eco-system.
Bio: Dr Vipul Patel is a senior technologist in Technology and Quality group in Cisco supporting Silicon Photonics product development. He cofounded Lightwire Inc in 2002 and joined Cisco through the Lightwire acquisition in early 2012. He is one of the key contributors in development of IEEE standards compliant CPAK 100G product series. Prior to Lightwire, Vipul was vice president of R&D at LightMatrix Technologies and group head in Sarnoff Labs. Vipul received his MS and PhD degrees in electrical engineering from New Jersey Institute of Technology in 1990 and 1993 respectively. He holds 78 US patents in the field of Silicon Photonics with additional 24 patent applications pending.
Highly Reliable Silicon Photonics DWDM modules
Ranjani Muthiah, Associate Vice President for Quality & Reliability, Inphi
ABSTRACT: Highly reliable Silicon Photonics-based modules are a key enabler for high-speed data transport in the cloud and datacenter markets. Inphi’s Silicon Photonics-based DWDM modules have been deployed in the field since 2017. A systematic, proactive approach to product qualification and reliability is essential to deliver highly reliable photonics modules for commercial deployment. Methodologies used in product design and manufacturing for quality and reliability of highly integrated photonics integrated circuits (PICs) in silicon will be reviewed. Accelerated stress testing strategies and their applicability to field use conditions will be discussed. Quality, reliability and field data on silicon photonics-based module products will be presented.
Bio: Ranjani Muthiah is Associate Vice President for Quality and Reliability at Inphi Corp. She is responsible for the quality of Inphi’s broad portfolio of IC and optical data communication products. Prior to joining Inphi in 2014, Ranjani was with Infinera as Sr. Manager, Reliability Engineering in the Optical Integrated Components Group. She has been instrumental in successfully productizing large scale photonic integrated circuit-based modules, in InP and Silicon platforms, with excellent reliability.
Ranjani received her Ph.D. in Materials Science & Engineering from the University of Pennsylvania and her B.Tech. in Metallurgical Engineering from the IIT-Varanasi, India. Dr. Muthiah has published over 25 papers in technical journals/conferences and is a co-inventor on multiple patents.
Reliability Challenges for Electronics and Photonics Packaging for Deep Space
Reza Ghaffarian, Ph.D., and John W. Evans, Ph.D., Jet Propulsion Laboratory, California Institute of Technology
ABSTRACT: The stringent reliability requirements for deep-space missions have not changed even though electronics technologies have astronomically advanced since NASA/JPL’s Voyager1 spacecraft that utilized a digital tape recorder (3×2.8 kbps/week) — built 43 years ago and in 2012, it crossed interstellar space. Advanced commercial high-density packages lack the reliability required for use in deep-space electronics because of shorter-life expectancy. However, significant improvements in electronics and photonics via tailoring have enabled unparallel progress in communication, high data rates, and autonomous controls for spacecrafts and rovers.
This talk will address aspects of reliability requirements and implementation for electronics packaging technologies and photonics systems for harsh environments of deep-space missions. It briefly reviews the status of single- and heterogenous-packaging technologies — More than Moore’s Law (MtM) — that now has been widely implemented to increase the capability of commercial electronics due to increasing costs and implementation limitations of Moore’s law for finer die features. It presents the thermal cycle reliability tests for a number of advanced electronics assemblies including package-on-package (PoP) and system-in-package (SiP). Results will include representative reliability test data and failure mechanisms of hardware exposed to extreme cold temperature of Mars down to –135℃ and cryogenic temperature of Jupiter’s moon, Europa, as cold as –240℃.
Bio: Dr. Reza Ghaffarian has more than 35 years of industrial and academic experience. For the last 26 years at NASA/JPL, he has led R&D reliability and quality assurance activities in advanced electronic packaging technologies and has been a subject-matter expert (SME) for most JPL spaceflight projects including the Mars 2020 Perseverance. He has received many awards including the NASA Exceptional Service Medal for outstanding leadership and industrial partnership, and the 2020 SMTA Founder’s Award for exceptional contributions to the industry, SMTA, and research in the area of reliability for years. He has authored more than 150 technical papers, 7 book chapters, two guidelines, and co-edited a CSP book. He serves as technical Advisor/Committee to IPC, Microelectronics Journal, SMTA, IMAPS and IEEE IEMT/EPS. He received his Ph.D. in 1982 from the University of California at Los Angeles (UCLA).
Evolution of Data Center Optics Packaging Technology and Reliability Challenges
Dr. Omer Khayam, Technical Infrastructure, Google
ABSTRACT: The unprecedented growth in cloud-based applications has transformed the traditional role of data centers to hyperscale computing environments with Petabits per second of bisection networking bandwidth connecting a large number of endpoint devices. To support the staggering growth of traffic at suitable power and cost points, optical interconnects have become an indispensable building block for the data center. Specifically, pluggable optical modules installed on the switch front plate have dominated intra-data center optics for over a decade. Form factor standardization has driven the low-cost, high-volume deployment of pluggable transceivers. With every generation, the front panel bandwidth density successfully scaled with the switch ASIC bandwidth while improving the energy efficiency and front panel linear density. The ease of serviceability and manufacturability played a key role in wide scale adoption. In order to continue scaling of the switch radix and bandwidth, the industry has more recently begun to investigate alternative solutions with tighter integration of optics and electronics. This talk reviews the historical success factors of pluggables, the packaging trends driving the next-generation of data center optics and some of the reliability challenges ahead.
Bio: Dr. Omer Khayam is with Google Technical Infrastructure where he is focused on the optical interconnect technologies for the data center. Prior to joining Google, Omer was at Infinera, where he was involved in the design, development and reliability qualification of industry leading coherent photonic integrated circuits (PIC). He received his B.S in Engineering from the GIK Institute, Pakistan and his Ph.D. degree from the Institut d’Optique, France.
Electronics Quality and Reliability for Critical Applications that Adopt New Technologies and Designs
Ravi Mahajan, Alan Lucero, and Joe Walczyk, Intel
ABSTRACT: Modern societies are accustomed to low-cost, ubiquitous applications and underlying technologies to enhance life experiences and increase productivity. People interact with each other, machines and technology using low-cost semiconductors that are efficient, sufficiently capable and short-lived. Networked computation and automated electronic-mechanical systems with a mix of heterogeneous technologies are expected to perform, be safe for humans and dependable for up to 15 yrs. The challenge for designers, manufacturers, test validators and technologists is to predict the dependability of the systems by adapting quality and reliability assessments and to qualify new products for known, unknown and changing uses. Failure-oriented acceleration testing, contemporary computational methods and field assessment can help respond to the challenge. Robustness testing and HALT/HASS potential enhancements are introduced for additional development. This presentation shows how adapted methods can be used to qualify safe and dependable products for their expected use while presenting methods to account for unexpected use.
Bio: Ravi Mahajan is an Intel Fellow responsible for Assembly and Packaging Technology Pathfinding for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives. He has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes including 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Ravi joined Intel in 1992 after earning his Ph.D. in Mechanical Engineering from Lehigh University. He holds the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights have led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques for thermo-mechanical stress model validation. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME, the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6 and most recently the 2020 Richard Chu ITherm Award For Excellence and the 2020 ASME EPPD Excellence in Mechanics Award. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. He has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE.
Bio: Alan Lucero is the Managing director for global quality, reliability and regulatory standardization at Intel. Alan is also the chairman of the JEDEC JC14 Quality & Reliability standards committee and a US delegate and a chairman in the International Electrotechnical (IEC) committee, TC47 semiconductor devices as well as an assigned expert delegate to TC91 assembly of devices. He was awarded the IEC 1917 Award for Exceptional Technical Achievement. Previously Alan managed the quality and reliability simulation group in technology development at Intel. Additionally he was part of the R&D team and Q&R management team that developed the first high-volume plastic flip-chip packages that spanned from 5 process generations from 90nm to 14nm. Alan holds 3 patents in areas of optical packaging interconnect, device damage sensors and use condition telemetry devices and methods. Alan joined Intel in 1996 with graduate degrees in Materials Science from the University of Illinois at Urbana-Champaign and undergrad degrees in Physics and Materials Engineering from New Mexico Inst. of Mining. Alan has taught professional development courses on semiconductor reliability engineering for over 10 years at Ariz. State Univ., IEEE-Int’l Reliability Physics Symposium and IEEE Electronic Components and Tech. Conf. He has 24 publications in areas ranging from Reliability to advanced liquid crystal polymer/films and synthesis of diamond films.
Bio: Joe Walczyk received his B.S. in Industrial and Manufacturing Engineering from Oregon State University. He joined Intel in 2004, after four years at Maxim Integrated Products as a Test Engineer. At Maxim, Joe specialized in RF product engineering and Advanced Tooling and Sort processes. Since joining Intel as a Sort/Test Engineer, he has held a variety of positions within the Assembly/Test Technology Development Organization (ATTD) organization. He has been responsible for delivering advanced thermal and mechanical technologies, including managing the Thermal-Mechanical Pathfinding team for 7yrs. His main interest is in innovation of new package and test technologies to continuously advance the current state of art. Joe is currently a Principal Engineer in ATTD driving Novel Assembly-Test Technologies. Highly passionate and motivated about innovation, Joe currently has 11 issued patents and with >10 more in process.
Reliability Challenges for the Aerospace Sector and the use of Commercial off-the-shelf Components (COTS)
Chris Bailey, University of Greenwich
ABSTRACT: The use of electronic components in the high-reliability aerospace sector represents less than 1% of the total component market, where the majority of packaged components are designed to meet the requirements of sectors where components are subjected to less-harsh environments and whose reliability and lifetime requirements are much less than the aerospace sector. Hence chip and package design companies are mainly focused on these main market sectors which unfortunately for the aerospace industry means that packaged component designs may not meet their full requirements. This requires aerospace companies and their supply chains to implement additional processes to ruggedise these packages so that risks of issues such as tin-whiskers can be mitigated.
This presentation will discuss these reliability challenges and demonstrate a combined modeling and test approach to address these issues at the early stages of design. For example, for leaded components and BGA components there is a requirement to ensure that the solder interconnects and surface finishes meet aerospace reliability standards, and this requires the use of refinishing processes such as hot solder dipping and solder re-balling. In addition to this, the assembly of these components onto circuit boards requires adoption of conformal coatings, edgebond materials, and other assembly materials to address the strict reliability requirements for aerospace electronics systems. The talk will discuss these additional processes for Leaded, QFN, and micro-BGA packages and demonstrate possible mitigation strategies that meet aerospace reliability requirements.
Bio: Professor Chris Bailey is President of the IEEE Electronics Packaging Society. He is also the Director of the Computational Mechanics and Reliability Group at the University of Greenwich, UK. He has a PhD in Computational Modeling and an MBA in Technology Management, and has published over 300 papers on Design and Simulation of Electronics Packaging. He has also secured over £5M of external funding from UK-Government, EU-Horizon 2020, DoD, and industry, and successfully supervised 22 Ph.D. students. Chris has served on several external government committees, which includes the 2014 UK Research Excellence Framework, to assess research outputs and research impact across UK universities. He is a member of the EPSRC College (UK Equivalent to NSF in USA); and associate editor for the IEEE Transactions of Components, Packaging, and Manufacturing Technology. He is also co-chair for the modeling and simulation technical working group on the new Heterogeneous Integration Roadmap.