IEEE ARGENCON 2020

Layout Engineer

Electronic Engineer, Electrical and Electronic Engineering · (2010 – 2015) Universidad Nacional del Sur

Allegro MicroSystems, LLC
Layout Engineer
Febrery  2016 – Present (4 years 10 month)
Buenos Aires, Argentina

Martín Di Federico received his B.S. degree in electronic engineering in 2006 from the Universidad Nacional del Sur (UNS), Argentina, and his Ph.D. degree in engineering in 2011 from the same University. He completed a Postdoctorate in “Electronic Circuits in 3D Technology with Applications to Vision”. He was a visitor schollar at the Sensory Communication & Microsystems Laboratory of the Johns Hopkins University and the Nanoelectronics and Gigascale Systems Laboratory at National Chiao Tung University in Tawian.
He Participated in more than 8 Research and Development Projects. He is the author or co-author of 5 Articles in International Journals, author of more than 19 papers published in National and International congresses. Co-Directed 4 final Career Projects, 2 Magisteres and a Doctorate. He was reviewer for several conferences such as ISCAS, LASCAS, IBERCHIP, Prime-LA, CAMTA, RPIC and CASE. He participated as an organizer in 4 Congresses and 3 Workshops. He was the Chair of LASCAS 2017 Conference.
He is an Assistant Investigator of CONICET from 2016 and Teacher Assistant in VLSI Circuits Design and Analog Circuits Design at UNS. He is currently lead of the Design and Verification of Mixed Signal Smart Circuits group in the in Micro and Nanoelectronics Research and Development Center (CMNB) of the National Institute of Industrial Technology (INTI). He was a BoG member of Circuits and Systems Society and the actual Argentina Chapter Chair of CASS. His current field of research is the applications of Digital and VLSI circuits for image sensing and processing. His research interests include digital image processing, CNNs, neuromorphic circuits.

Gilson I. Wirth received the B.S.E.E and M.Sc. degrees from the Universidade Federal do Rio Grande do Sul,Brazil, in 1990 and 1994, respectively. In 1999 he received the Dr.-Ing. degree in Electrical Engineering from the University of Dortmund, Dortmund, Germany.

He is currently a professor at the Electrical Engineering Department at the Universidade Federal do Rio Grande do Sul – UFRGS (since January 2007).

From 2000 to 2002 he worked as lecturer and researcher in the field of microelectronics at the Informatics Institute, Universidade Federal doRio Grandedo Sul (UFRGS).

From July 2002 to December 2006 he was professor and head of the Computer Engineering Department, Universidade Estadual doRio Grandedo Sul (UERGS). He founded the research group in micro- and nano-electronics at UERGS.

In July, August and December 2001 he was at Motorola,Austin,Texas, leading the team working in CMOS process technology transfer to CEITEC,Porto Alegre,Brazil. The technology transfer was funded by FAPERGS under grant number 01/1093.3 (first phase of technology transfer) and 01/1628.9 (second phase of technology transfer).

In February and March 2002 he was at the Corporate Research Department of Infineon Technologies,Munich,Germany, working as guest researcher on low-frequency noise in deep submicron MOS devices.

His research work is focused on reliability and yield of MOS devices and circuits, including low-frequency noise, bias temperature instability (BTI), radiation effects, and design techniques to improve yield and reliability.

Marcelo Antonio Pavanello received the Electrical Engineering degree from FEI University in 1993, receiving the award “Instituto de Engenharia” given for the best student among all the modalities of engineering programs offered at FEI. He received the M. Sc. and Ph. D. degrees in 1996 and 2000, respectively, in Electrical Engineering (Microelectronics) from University of São Paulo, Brazil. From August to December 1998 he was with Laboratoire de Microélectronique from Université Catholique de Louvain (UCL), Belgium, working in the fabrication and electrical characterization of novel channel-engineered Silicon-On-Insulator (SOI) transistors. From 2000 to 2002 he was with the Center of Semiconductor Components and Nanotechnologies, State University of Campinas, Brazil, where he worked as a post-doctoral researcher in the development of a CMOS n-well process. Since 2003 he joined FEI University, where he is now Full Professor at Electrical Engineering Department. In 2008 he has been with UCL as a visiting professor. Between 2010 and 2020 he also served as Vice-Rector for Teaching and Research at FEI.

Dr. Pavanello is Senior Member of the IEEE and Brazilian Microelectronics Society. He is also Researcher Associated to the National Council for Scientific Development (CNPq), Brazil. Since 2007 he serves as IEEE Electron Devices Society (EDS) Distinguished Lecturer and has been nominated to the Compact Modeling Technical Committee (CMTC) of EDS in 2018. In 2019 he has been assigned as Editor for Process and Device Modeling of IEEE Transactions on Electron Devices journal.

He is author or co-author of more than 300 technical papers in peer-reviewed journals and conferences, and author/editor of 6 books. Dr. Pavanello coordinates several research projects fomented by Brazilian agencies like FAPESP, CNPq and Capes. He also supervised several PhD dissertations, MSc thesis and undergraduate projects in Electrical Engineering.

His current interests are the compact modeling, fabrication, electrical characterization and simulation of SOI CMOS transistors with multiple gate configurations and silicon nanowires; the wide temperature range of operation of semiconductor devices; the digital and analog operation of novel channel-engineered SOI devices and circuits.